The subject application is related to subject matter disclosed in the Japanese Patent Application No.Hei11-261014 filed in Sep. 14, 1999 in Japan, to which the subject application claims priority under the Paris Convention and which is incorporated by reference herein.
1. Field of the Invention
The present invention is related to a gated clock design technique by the use of a computer, and more particularly related to a computer aided design system for clock gated logic circuits, a computer-readable medium for storing the program of the system and a gated clock circuit.
2. Prior Art
In recent years, the frequencies of the clock signal for driving LSIs have been dramatically increased to require much power consumption.
The gated clock design technique has been developed for the purpose of obtaining the logic circuit designs with low electric power consumption. The procedure of modifying logic circuits by means of the gated clock design technique is called as xe2x80x9cclock gatingxe2x80x9d in the following explanation.
FIG. 1(a) is a circuit diagram showing a clocked logic circuit with a clock tree structure which has not been clock gated. In the followings, registers to be controlled under the same register transfer condition (the same enable logic) are grouped into a set which is called a xe2x80x9cclusterxe2x80x9d for the sake of explanation. Also, in this example, there are ten register transfer conditions. Each register is subjected to one of the register transfer conditions and belongs to a corresponding one of the ten clusters C0 to C9.
Since the circuit as illustrated in FIG. 1(a) is not designed in the clock gating structure, the clock signal CLK is supplied to all the clusters through the clock tree structure T in which the load is distributed uniformly. It is possible therefore to minimize the clock skew and therefore to finish the designing and developing process of an error free circuit in a short time within the schedule.
However, in the recent years, since the frequency of the clock signal CLK has been dramatically increased to require much power consumption so that the increase of the electric power consumption becomes problematic in the case of the logic circuit as illustrated in FIG. 1(a). Furthermore, as illustrated in FIG. 1(b) which is a circuit diagram showing one register circuit for use in the clock tree structure of the clocked logic circuit which has not been clock gated, a feedback loop including a multiplexer 22 has to be provided for each register circuit in order to keep the current value in the register 21 when the register transfer condition is not satisfied. In this case, since the clock signal CLK is supplied always to all the register circuits to drive the entirety of the clock tree structure, the electric power consumption becomes significantly increased.
Because of this, such a circuit as described above is quite inappropriate to be applied for electric appliances powered by batteries such as mobile gears which are driven for short times after charging. It is therefore required to reduce the electric power consumption of the circuit.
In usual cases, it is believed effective to reduce the electric power consumption of the clock supply system for the purpose of reducing the electric power consumption of an LSI chip. The clock gating technique has been known as a most effective technique to reduce the electric power consumption of the clock supply system.
FIG. 2(a) is a circuit diagram showing an exemplary configuration of the clock tree structure of a gated clock logic circuit in accordance with a conventional technique. Register circuits belong to ten clusters and then belong respectively to ten partial trees T0 to T9, to which a clock signal CLK is supplied through AND gate circuits G0 to G9 provided for clock gating. The clock signal CLK is supplied to the AND gate circuits G0 to G9 through a buffer circuit 1.
For example, since the register transfer condition En(C6) is input to one input terminal of the AND gate circuit G6, the clock signal CLK is supplied to the partial tree T6 when this register transfer condition (i.e. En(C6)=1) is satisfied while the clock signal CLK is not supplied to the partial tree T6 when this register transfer condition is not satisfied (i.e. En(C6)=0).
In this case, since there are 611 register circuits belonging to the cluster C6 to which the clock signal CLK is supplied only when the register transfer condition is satisfied, it is possible to keep the current value in the register 21 when the register transfer condition is not satisfied even if there is provided no feedback loop for the register circuit 2 as illustrated in FIG. 2(b) resulting in a simplified circuit design.
Namely, in the case of the gated clock logic circuit in accordance with the conventional technique as illustrated in FIG. 2(a), since clock signal CLK is supplied to the register circuits only when the register transfer condition is satisfied, there is no need for the feedback loops to keep the current values in the registers as illustrated in FIG. 1(b) when the register transfer condition is not satisfied so as to reduce the unnecessary clock pluses of supplying the clock signal to the register circuits, the unnecessary clock pluses of driving the clock tree structure and therefore the electric power consumption thereof.
However, the clock tree structure is composed of the combination of the partial trees for the respective clusters which have different numbers of the register circuits belonging thereto. For example, the differential number between the constituent register circuits of the partial tree T0 and the partial tree T6 is significant, i.e., 572, and therefore it is difficult to keep the clock skew within a tolerable range. As a result, when the skew is substantial, there is a problem that the risk of device malfunctions is increased to require the designer to begin his work again so as to elongate the designing and development time.
The present invention has been made in order to solve the shortcomings as described above. It is an object of the present invention to provide a receiver/transmitter apparatus which can be manufactured in massproduction at a low cost.
In brief, the above and other objects and advantages of the present invention are provided by a new and improved gated clock circuit comprising:
a plurality of storage elements which are grouped into a plurality of partial trees;
a plurality of gating circuits provided respectively for said partial trees in order to control the supply of a clock signal to each of said partial trees respectively in accordance with the logic sum of the enable logics of those of said storage elements belonging to said each of said partial trees,
wherein at least one of said partial trees has at least one of said storage elements having a feedback loop and at least one of said storage elements having no feedback loop.
In a preferred embodiment, further improvement resides in that said storage elements are grouped into the plurality of partial trees in order that the disparity in the numbers of said storage elements belonging to said partial trees is no higher than 5%.
In a preferred embodiment, further improvement resides in that said storage elements are register circuits consisting of flip-flops.
In a preferred embodiment, further improvement resides in that said feedback loop is composed of a multiplexer for selecting either of the output signal of said register circuit and the external input signal and outputting the signal as selected to said register circuit in accordance with the enable logic of the group including the storage element having that feedback loop.
In accordance with a further aspect of the present invention, the above and other objects and advantages of the present invention are provided by a new and improved computer aided design system for clock gated logic circuits consisting of a plurality of storage elements, said system comprising:
a circuit information storing section for storing information about a clock gated logic circuit under the design;
a storage element allocation section for allocating said storage elements to a plurality of partial trees on the basis of said information about a clock gated logic circuit said gated clock circuit under the design;
an output section for outputting clock tree structure information with gating logics under the design on the basis of said partial trees consisting of said storage elements as allocated by said storage element allocation section;
wherein at least one of said partial trees has at least one of said storage elements having a feedback loop and at least one of said storage elements having no feedback loop.
In a preferred embodiment, further improvement resides in that said circuit information storing section serves to store clock tree structure information without gating logics as said information about the clock gated logic circuit under the design.
In a preferred embodiment, further improvement resides in that said storage elements are allocated to the plurality of partial trees in order that the disparity in the numbers of said storage elements belonging to said partial trees is no higher than 5%.
In a preferred embodiment, further improvement resides in that said gating logics are provided to control the supply of the clock signal to said partial trees in accordance with the logic sum of the enable logics of those of said storage elements belonging to said each of said partial trees.
In a preferred embodiment, further improvement resides in that, while said storage element allocation section serves to generate a plurality of allocation patterns according to each of which said storage element are allocated to said partial trees in a different manner, said output section serves to output one of said allocation patterns taking into consideration the electric power consumption of the gated clock circuit as constructed in accordance with each allocation pattern.
In accordance with a further aspect of the present invention, the above and other objects and advantages of the present invention are provided by a new and improved computer program embodied on a computer-readable medium for designing clock gated logic circuits, said program comprising:
a step of obtaining information about a clock gated logic circuit under the design;
a step of allocating said storage elements to a plurality of partial trees on the basis of said information about a clock gated logic circuit said gated clock circuit under the design;
a step of outputting clock tree structure information with gating logics under the design on the basis of said partial trees consisting of said storage elements as allocated by said allocating step,
wherein at least one of said partial trees has at least one of said storage elements having a feedback loop and at least one of said storage elements having no feedback loop.
In a preferred embodiment, further improvement resides in that said information about the clock gated logic circuit under the design includes clock tree structure information without gating logics.
In a preferred embodiment, further improvement resides in that said storage elements are allocated to the plurality of partial trees in order that the disparity in the numbers of said storage elements belonging to said partial trees is no higher than 5%.
In a preferred embodiment, further improvement resides in that said gating logics are provided to control the supply of the clock signal to said partial trees in accordance with the logic sum of the enable logics of those of said storage elements belonging to said each of said partial trees.
In a preferred embodiment, further improvement resides in that, while a plurality of allocation patterns are generated, according to each of which patterns said storage element are allocated to said partial trees in a different manner, one of said allocation patterns is selectively output, taking into consideration the electric power consumption of the gated clock circuit as constructed in accordance with each allocation pattern.